如何用VHDL语言设计四位全加器答:VHDL语言设计四位全加器:library IEEE;use IEEE.Std_logic_1164.ALL;entity pro1 is port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);end pro1;architecture pro1_arch of pro1 is begin Y10<='0' when(B0='0') and ((A0='0')...