刚学习verilog,用modulesim软件,写一个一位全加器程序,写完了怎么赋...答:写个.vt程序:`timescale 1ps/1ps module sim();rega,b,c_in;wiresum,c_out;initial begin a <= 0;b <= 0;c_in <= 0;end always #10 a <= ~a;always #15 b <= ~b;always #25 c_in <= ~c_in;fulladdU(sum,c_out,a,b,c_in);endmodule ps:你的程序有误,c未定义,...