用VHDL写一个有七位（每个5bits）输入，三位控制信号的选择器。

老师要求必须用两种方式写出 behavior的方法很简单，几个case就搞定了。
关键现在的难点在于必须用structure来写出architecture。
我现在的思路是
定义7个输入位ABCDEFG，三位的选择输入端S0、S1、S2.一个 5位输出端OK1=A与（S0非S1非S2非）K2=B与（S0非S1非S2）K3=C与（S0非S1S2非）K4=D与（S0非S1S2）K5=E与（S0S1非S2非）K6=F与（S0S1非S2)K7=G与（S0S1S2非）O=K1或K2或K3或K4或K5或K6或K7这样子的方法有几个问题，第一个如果输入信号是1bit的话我这个是成立的但是我现在是5bits，这时候我就需要用到A1A2A3A4A5B1B2B3B3B4B5。。。。O1O2O3O4O5每个都需要进行上述的逻辑运算。这样的话我的entity部分的定义就很复杂了。再者如果这个成立，我的behavior和structure就不能共用一个testbench了。

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其他回答

第1个回答推荐于2016-08-08

----注：本工程为用structure方法实现多路选择
----Date: 2013-09-25-
----Author： Mabs
-----------------------------------------------------------------------------------
-------与门------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity and_ab is
port(

A,B : in std_logic;
C : out std_logic
);
architecture bhv of and_ab is
begin

C <= B and A;
end bhv;
-----------------------------------------------------------------------------------
-------或门------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity or_ab is
port(

A,B : in std_logic;
C : out std_logic
);
architecture bhv of or_ab is
begin

C <= B or A;
end bhv;
-----------------------------------------------------------------------------------
-------非门------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity not_a is
port(

A : in std_logic;
C : out std_logic
);
architecture bhv of not_a is
begin

C <= not A;
end bhv;
-----------------------------------------------------------------------------------
-------3input与门------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity and3_abc is
port(

A,B,C : in std_logic;
D : out std_logic
);
architecture bhv of and3_abc is
component and_ab is

port(
A,B : in std_logic;
C : out std_logic
);
end component;
signal tmp : std_logic;
begin
u1_and: and_ab

port map
( A => A,
B => B,
C => tmp
);
u2_and: and_ab
port map

( A => C,
B => tmp,
C => D
);
end bhv;
-----------------------------------------------------------------------------------

-------7input或门------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity or7_abc is
port(

A,B,C,D,E,F,G : in std_logic;
H : out std_logic
);
architecture bhv of or7_abc is
component or_ab is

port(
A,B : in std_logic;
C : out std_logic
);
end component;
signal tmpAB,tmpABC,tmpABCD,tmpABCDE,tmpABCDEF : std_logic;
begin
u1_or: or_ab

port map
( A => A,
B => B,
C => tmpAB
);
u2_or: or_ab
port map

( A => C,
B => tmpAB,
C => tmpABC
);
u3_or: or_ab

port map
( A => D,
B => tmpABC,
C => tmpABCD
);
u4_or: or_ab
port map

( A => E,
B => tmpABCD,
C => tmpABCDE
);
u5_or: or_ab

port map
( A => F,
B => tmpABCDE,
C => tmpABCCDEF
);
u6_or: or_ab

port map
( A => G,
B => tmpABCDEF,
C => H
);
end bhv;

-----------------------------------------------------------------------------------

----main-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.pkg;

entity 7sel_to1 is
port(
Din1,Din2,Din3,Din4,Din5,Din6,Din7 : in std_logic_vector(4 downto 0);
S1,S2,S3 : in std_logic;
Dout : out std_logic_vector(4 downto 0)
);

architecture bhv of 7sel_to1 is
component and_ab is
port(

A,B : in std_logic;
C : out std_logic
);
end component;
component or_ab is
port(

A,B : in std_logic;
C : out std_logic
);
end component;
component not_a is

port(
A : in std_logic;
C : out std_logic
);
end component;
component and3_abc is
port(

A,B,C : in std_logic;
D : out std_logic
);
end component;
component or7_abc is
port(

A,B,C,D,E,F,G : in std_logic;
H : out std_logic
);
signal tmp1,tmp2,tmp3,tmp4,tmp5,tmp6,tmp7 : std_logic_vector(4 downto 0);
signal nS1,nS2,nS3 : std_logic;

signal sel1,sel2,sel3,sel4,sel5,sel6,sel7 : std_logic;
begin
---not--------------

u1_not_S1: not_a
port map(
A=>S1,
C=>nS1
);
u2_not_S2: not_a
port map(

A=>S2,
C=>nS2
);
u3_not_S3: not_a
port map(

A=>S3,
C=>nS3
);
---3and---------------
u1_and_nS1nS2nS3: and3_abc
port map(

A=>nS1,
B=>nS2,
C=>nS3,
D=>sel1
);
u2_and_nS1nS2S3: and3_abc
port map(
A=>nS1,
B=>nS2,
C=>S3,
D=>sel2
);
u3_and_nS1S2nS3: and3_abc
port map(
A=>nS1,
B=>S2,
C=>nS3,
D=>sel3
);
u4_and_nS1S2S3: and3_abc
port map(
A=>nS1,
B=>S2,
C=>S3,
D=>sel4
);
u5_and_S1nS2nS3: and3_abc
port map(
A=>S1,
B=>nS2,
C=>nS3,
D=>sel5
);
u6_and_S1nS2S3: and3_abc
port map(
A=>S1,
B=>nS2,
C=>S3,
D=>sel6
);
u7_and_S1S2nS3: and3_abc
port map(
A=>S1,
B=>S2,
C=>nS3,
D=>sel7
);
------------------------
---and0---------------------
u1_and0: and_ab
port map
( A => sel1,
B => Din1(0),
C => tmp1(0)
);
u2_and0: and_ab
port map

( A => sel2,
B => Din2(0),
C => tmp2(0)
);
u3_and0: and_ab
port map

( A => sel3,
B => Din3(0),
C => tmp3(0)
);
u4_and0: and_ab
port map

( A => sel4,
B => Din4(0),
C => tmp4(0)
);
u5_and0: and_ab
port map

( A => sel5,
B => Din5(0),
C => tmp5(0)
);
u6_and0: and_ab
port map

( A => sel6,
B => Din6(0),
C => tmp6(0)
);
u7_and0: and_ab
port map

( A => sel7,
B => Din7(0),
C => tmp7(0)
);
------------------------
-----1-------------------
u1_and1: and_ab
port map
( A => sel1,
B => Din1(1),
C => tmp1(1)
);
u2_and1: and_ab
port map

( A => sel2,
B => Din2(1),
C => tmp2(1)
);
u3_and1: and_ab
port map

( A => sel3,
B => Din3(1),
C => tmp3(1)
);
u4_and1: and_ab
port map

( A => sel4,
B => Din4(1),
C => tmp4(1)
);
u5_and1: and_ab
port map

( A => sel5,
B => Din5(1),
C => tmp5(1)
);
u6_and1: and_ab
port map

( A => sel6,
B => Din6(1),
C => tmp6(1)
);
u7_and1: and_ab
port map

( A => sel7,
B => Din7(1),
C => tmp7(1)
);
------------------------
----2--------------------
u1_and2: and_ab
port map
( A => sel1,
B => Din1(2),
C => tmp1(2)
);
u2_and2: and_ab
port map

( A => sel2,
B => Din2(2),
C => tmp2(2)
);
u3_and2: and_ab
port map

( A => sel3,
B => Din3(2),
C => tmp3(2)
);
u4_and2: and_ab
port map

( A => sel4,
B => Din4(2),
C => tmp4(2)
);
u5_and2: and_ab
port map

( A => sel5,
B => Din5(2),
C => tmp5(2)
);
u6_and2: and_ab
port map

( A => sel6,
B => Din6(2),
C => tmp6(2)
);
u7_and2: and_ab
port map

( A => sel7,
B => Din7(2),
C => tmp7(2)
);
------------------------
----3--------------------
u1_and3: and_ab
port map
( A => sel1,
B => Din1(3),
C => tmp1(3)
);
u2_and3: and_ab
port map

( A => sel2,
B => Din2(3),
C => tmp2(3)
);
u3_and3: and_ab
port map

( A => sel3,
B => Din3(3),
C => tmp3(3)
);
u4_and3: and_ab
port map

( A => sel4,
B => Din4(3),
C => tmp4(3)
);
u5_and3: and_ab
port map

( A => sel5,
B => Din5(3),
C => tmp5(3)
);
u6_and3: and_ab
port map

( A => sel6,
B => Din6(3),
C => tmp6(3)
);
u7_and3: and_ab
port map

( A => sel7,
B => Din7(3),
C => tmp7(3)
);
------------------------
----4--------------------
u1_and4: and_ab
port map
( A => sel1,
B => Din1(4),
C => tmp1(4)
);
u2_and4: and_ab
port map

( A => sel2,
B => Din2(4),
C => tmp2(4)
);
u3_and4: and_ab
port map

( A => sel3,
B => Din3(4),
C => tmp3(4)
);
u4_and4: and_ab
port map

( A => sel4,
B => Din4(4),
C => tmp4(4)
);
u5_and4: and_ab
port map

( A => sel5,
B => Din5(4),
C => tmp5(4)
);
u6_and4: and_ab
port map

( A => sel6,
B => Din6(4),
C => tmp6(4)
);
u7_and4: and_ab
port map

( A => sel7,
B => Din7(4),
C => tmp7(4)
);
------------------------
--===========================
u1_or: or7_abc

port map
( A => tmp1(0),
B => tmp2(0),
C => tmp3(0),
D => tmp4(0),
E => tmp5(0),
F => tmp6(0),
G => tmp7(0),
H => Dout(0)
);
u2_or: or7_abc

port map
( A => tmp1(1),
B => tmp2(1),
C => tmp3(1),
D => tmp4(1),
E => tmp5(1),
F => tmp6(1),
G => tmp7(1),
H => Dout(1)
);
u3_or: or7_abc
port map

( A => tmp1(2),
B => tmp2(2),
C => tmp3(2),
D => tmp4(2),
E => tmp5(2),
F => tmp6(2),
G => tmp7(2),
H => Dout(2)
);
u4_or: or7_abc
port map

( A => tmp1(3),
B => tmp2(3),
C => tmp3(3),
D => tmp4(3),
E => tmp5(3),
F => tmp6(3),
G => tmp7(3),
H => Dout(3)
);
u5_or: or7_abc

port map
( A => tmp1(4),
B => tmp2(4),
C => tmp3(4),
D => tmp4(4),
E => tmp5(4),
F => tmp6(4),
G => tmp7(4),
H => Dout(4)
);
--=============================
end bhv;本回答被提问者采纳

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