用VHDL 设计一个8选1的选择器 谢谢

Question

用VHDL 设计一个8选1的选择器
要求该选择器的被选择对象和输出对象都是4位二进制码数据(用调用函数发)

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity mux8_1 is
port
(
D0,D1,D2,D3,D4,D5,D6,D7: in std_logic_vector(3 downto 0);
A : in std_logic_vector(2 downto 0);
CS : in std_logic;
DOUT : out std_logic_vector(3 downto 0)
);
end mux8_1;

architecture rt1 of mux8_1 is
begin
process(D0,D1,D2,D3,D4,D5,D6,D7,A,CS)
begin
if CS = '1' then
DOUT <= "0000";
else
case A is
when "000" => DOUT <= D0;
when "001" => DOUT <= D1;
when "010" => DOUT <= D2;
when "011" => DOUT <= D3;
when "100" => DOUT <= D4;
when "101" => DOUT <= D5;
when "110" => DOUT <= D6;
when "111" => DOUT <= D7;
when others=> DOUT <= "0000";
end case;
end if;
end process;
end rt1;追问

调用函数 ？

追答

哦，没看清。