怎样用vhdl语言把100Mhz的频率变成1ms,我要程序.急！

Question

如题所述

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenpin is
port(clk: in std_logic;
clkout: out std_logic);
end;
architecture one of fenpin is
signal m: std_logic;
begin
process(clk)
variable q: integer range 500000 downto 0;
begin
if clk'event and clk='1' then q:=q+1;
if q=499999 then q:=0;m<=not m;
end if;
end if;
end process;
clkout<=m;
end;本回答被提问者采纳