VHDL 16选1数据选择器 用case语句

Question

如题所述

Answer 1

LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY mux_16_1 IS
PORT(en: IN Std_logic;
sel: IN Std_logic_vector(3 DOWNTO 0);
in_signal: IN Std_logic_vector(15 DOWNTO 0);
y: OUT Std_logic);
END mux_16_1;
ARCHITECTURE behavl_case OFmux_16_1 IS
BEGIN
p_case: PROCESS（en, sel, in_signal）
BEGIN
IF en='1' THEN
CASE sel IS
WHEN "0000" => y <= in_signal(0);
WHEN "0001" => y <= in_signal(1);
WHEN "0010" => y <= in_signal(2);
WHEN "0011" => y <= in_signal(3);
WHEN "0100" => y <= in_signal(4);
WHEN "0101" => y <= in_signal(5);
WHEN "0110" => y <= in_signal(6);
WHEN "0111" => y <= in_signal(7);
WHEN "1000" => y <= in_signal(8);
WHEN "1001" => y <= in_signal(9);
WHEN "1010" => y <= in_signal(10);
WHEN "1011" => y <= in_signal(11);
WHEN "1100" => y <= in_signal(12);
WHEN "1101" => y <= in_signal(13);
WHEN "1110" => y <= in_signal(14);
WHEN "1111" => y <= in_signal(15);
WHEN OTHERS => y <= 'Z';
END CASE;
ELSE
y <= 'Z';
END IF;
END PROCESS p_case;
END behavl_case;