用门电路实现一位全加器要怎么做，逻辑图要怎样画！谢谢！

Question

用译码器或者数据选择器实现的也可以

Answer 1

用verilog编写的数据选择器：
module multiplexer8_to_1(OUT,A2,A1,A0,D7,D6,D5,D4,D3,D2,D1,D0);
output OUT;
reg OUT;
input D7,D6,D5,D4,D3,D2,D1,D0;
input A2,A1,A0;
always@(A2,A1,A0,D0,D1,D2,D3,D4,D5,D6,D7)
case({A2,A1,A0})
3'd0:OUT=D0;
3'd1:OUT=D1;
3'd2:OUT=D2;
3'd3:OUT=D3;
3'd4:OUT=D4;
3'd5:OUT=D5;
3'd6:OUT=D6;
3'd7:OUT=D7;
default:$display("Unspecified control signal");
endcase
endmodule

module stimulus;
reg a2,a1,a0;

reg d7,d6,d5,d4,d3,d2,d1,d0;

wire out;

multiplexer8_to_1 mymux(out,a2,a1,a0,d7,d6,d5,d4,d3,d2,d1,d0);
initial
begin
d7=1;d6=1;d5=0;d4=0;d3=1;d2=0;d1=1;d0=0;
#10 $display (" d7=%b,d6=%b,d5=%b,d4=%b ,d3=%b,d2=%b,d1=%b,d0=%b\n", d7,d6,d5,d4,d3,d2,d1,d0);
a2=0;a1=0;a0=0;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out );
a2=0;a1=0;a0=1;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=0;a1=1;a0=0;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=0;a1=1;a0=1;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=1;a1=0;a0=0;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=1;a1=0;a0=1;

#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=1;a1=1;a0=0;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);
a2=1;a1=1;a0=1;
#10 $display("a2=%b,a1=%b,a0=%b,out=%b\n",a2,a1,a0,out);

end

endmodule本回答被提问者采纳