关于FPGA的CLK引脚,DataSheet上是这样说的:
CLK[0,2,4,6,9,11,13,15],DIFFCLK_[0..7]p ——Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins.
CLK[1,3,5,7,8,10,12,14],DIFFCLK_[0..7]n——Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins.
Positive、negative指的是什么意思,必须要成对使用吗?如果我把它当做普通输入接口用,要不要特殊考虑一些条件?