A multi-architecture signal-profile optimized final addition is used to compensate the delay profile. A low area/power consuming ripple carry adder (RCA) is used for bits (7:0), a variable block carry-select type adder (CSLA) is preferred for bits (23:8) and a conditional carry adder (CCA) is used for bits (31:24). Our CSLA is divided into sectors of lengths 1, 2, 3, 4 and 6, proceeding from the least significant to the most significant bit to operate faster.