用VHDL设计8路16位二进制八选一数据选择器！急！！！

Question

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Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity 8sel_to1 is
port(
clk: in std_logic;
ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8:in std_logic_vector(15 downto 0);
sel:in std_logic_vector(2 downto 0);
Dout:out std_logic_vector(15 downto 0)
);
end 8sel_to1;

architecture bhv of 8sel_to1is

begin
process(clk,sel)
begin
if (clk'event and clk='1') then
case sel is
when "000" => Dout<=ch1;
when "001" => Dout<=ch2;
when "010" => Dout<=ch3;
when "011" => Dout<=ch4;
when "100" => Dout<=ch5;
when "101" => Dout<=ch6;
when "110" => Dout<=ch7;
when "111" => Dout<=ch8;
when others=> Dout<=ch1;
end case;
end if;
end process;
end bhv;
--==========================================
library ieee;
use ieee.std_logic_1164.all;

entity 8sel_to1 is
port(
clk: in std_logic;
ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8:in std_logic_vector(15 downto 0);
sel:in std_logic_vector(2 downto 0);
Dout:out std_logic_vector(15 downto 0)
);
end 8sel_to1;

architecture bhv of 8sel_to1is
begin
Dout<= ch1 when sel="000" else
ch2 when sel="001" else
ch3 when sel="010" else
ch4 when sel="011" else
ch5 when sel="100" else
ch6 when sel="101" else
ch7 when sel="110" else
ch8 when sel="111" else
ch1;
end bhv;

Answer 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EightSOne is
port(clk: in std_logic;
a,b,c,d,e,f,g,h:in std_logic_vector(15 downto 0);
sel:in std_logic_vector(2 downto 0);
putout:out std_logic_vector(15 downto 0)
);
end EightSOne;

architecture Behavioral of EightSOne is

begin
process(clk,sel)
begin
if (clk'event and clk='1') then
case sel is
when "000" => putout<=a;
when "001" => putout<=b;
when "010" => putout<=c;
when "011" => putout<=d;
when "100" => putout<=e;
when "101" => putout<=f;
when "110" => putout<=g;
when "111" => putout<=h;
when others=>null;
end case;
end if;
end process;
end Behavioral;本回答被网友采纳